This invention relates to a improved process for patterning films used in the manufacture of integrated circuit structures. More particularly, this invention relates to an improved process for patterning films which may be used in the manufacture of emitter and gate electrodes respectively for bipolar and MOS integrated circuit structures.
2. Description of the Related Art
As integrated circuit structures become more complex and the density of the circuitry on chips increases, attention has been directed toward increasing the speed of individual devices used in the structure.
This, in turn, has lead to the development of processes to provide more precise alignment of the elements comprising the device, including self-alignment techniques to achieve, among other things, better control of the capacitance between elements of a device in view of the negative impact on speed which high interelectrode capacitance will produce.
Ho et al U.S. Pat. No. 4,381,953 describe a method for making a self-aligned bipolar transistor on a silicon substrate having a buried collector layer and an epitaxial layer thereon of a first conductivity type with an oxide isolation region formed between a collector sinker to the buried collector layer and the base/emitter portions of the transistor.
The Ho et al process includes the steps of depositing a doped polysilicon layer on the exposed epitaxial surface with the dopant being of opposite conductivity to the conductivity of the epitaxial layer; depositing a layer of silicon dioxide on the doped polysilicon layer; depositing a layer of photoresist on the oxide and masking off an intended intrinsic base region; using the resist as a mask, reactive ion etching away the oxide and polysilicon over the intended intrinsic base region; ion implanting the exposed intrinsic base region with ions of the first conductivity type; depositing an oxide layer on the exposed surface; reactive ion etching an emitter opening through the oxide layer and on the epitaxial surface above the implanted intrinsic base region; ion implanting the emitter region with ions of the opposite conductivity type; and then using a common heat cycle to anneal the ion implantations and drive in the emitter, intrinsic base, extrinsic base, and collector sinker.
Kayanuma et al U.S. Pat. No. 4,584,055 discloses a modified process for opening the window to the substrate for the base implant using a combination of reactive ion etching and selective wet etching to remove the overlying polysilicon using the Miller indices of the single silicon substrate to provide an etch stop for the wet etching.
While the above described processes can result in the formation of a satisfactory product, the reactive ion etching steps carried out, for example, over the emitter/base region of the substrate (or similarly, over the channel region of an MOS device, or the region of a substrate where a Schottky diode junction or a resistor will be formed), may result in damage to the substrate, including the epitaxial layer resulting in increased leakage and non-repeatable characteristics of devices fabricated in this manner. It would be desirable to provide a process for patterning films or layers on integrated circuit structures, without the use of reactive ion type dry etching techniques at those steps in the process when damage to the underlying material may occur.